Features

Valid-ready pipeline

Make your circuits valid-ready with a single click. Highlight your finished circuit with your cursor, right click, and select the “Make valid ready” button.

We have made this feature possible with our open-source circuit repository.

Smart complete

For the past month, we have collected a vast amount of SystemVerilog ciruits from our open source initiative, openchips. You can access these circuits directly with VScode’s auto-complete menu.

Instantiate snippet by calling !IC_mac

mac.v
module DW02_mac_inst(
    inst_A, 
    inst_B, 
    inst_C, 
    inst_TC, 
    MAC_inst 
);

  // Parameter definitions for input widths
  parameter A_width = 8;
  parameter B_width = 8;

  // Input and output port declarations
  input [A_width-1 : 0] inst_A;
  input [B_width-1 : 0] inst_B;
  input [A_width+B_width-1 : 0] inst_C;
  input inst_TC;
  output [A_width+B_width-1 : 0] MAC_inst;

  // Instance of DW02_mac
  DW02_mac #(A_width, B_width)
    U1 (
      .A(inst_A),
      .B(inst_B),
      .C(inst_C),
      .TC(inst_TC),
      .MAC(MAC_inst)
    );

endmodule

Instantiate snippet by calling !IC_vector_adder

vector_adder.v
module custom_vector_adder #(
    parameter NUM_INPUTS = 8,
    parameter INPUT_WIDTH = 8
)(
    input wire [NUM_INPUTS*INPUT_WIDTH-1:0] inst_INPUT,
    output wire [INPUT_WIDTH-1:0] SUM_inst
);

    // Internal signal to hold the sum
    reg [INPUT_WIDTH-1:0] sum;


    integer i;
    always @(*) begin
        sum = 0;
        for (i = 0; i < NUM_INPUTS; i = i + 1) begin
            sum = sum + inst_INPUT[i*INPUT_WIDTH +: INPUT_WIDTH];
        end
    end

    assign SUM_inst = sum;

endmodule

Instantiate snippet by calling !IC_cmp2_inst

cmp2_inst.v
module DW01_cmp2_inst(
  inst_A,
  inst_B,
  inst_LEQ,
  inst_TC,
  LT_LE_inst,
  GE_GT_inst
);

  parameter width = 8;

  input [width-1 : 0] inst_A;
  input [width-1 : 0] inst_B;
  input inst_LEQ;
  input inst_TC;
  output LT_LE_inst;
  output GE_GT_inst;

  // Instance of DW01_cmp2
  DW01_cmp2 #(width)
    U1 ( .A(inst_A), .B(inst_B), .LEQ(inst_LEQ), .TC(inst_TC),
        .LT_LE(LT_LE_inst), .GE_GT(GE_GT_inst) );

endmodule

You may contribute to our open-source repository here

Introduction

VPM

Verilog Modules

Valid-ready pipeline

Smart complete

Introduction

VPM

Verilog Modules

​Valid-ready pipeline

​Smart complete

Valid-ready pipeline

Smart complete