Command Documentation
List of VPM commands and usage.
Command Index
Lite Commands
Additional Pro Commands
Command Details
include
Usage: vpm include <MODULE_URL> [--repo] [--riscv] [--commit <HASH>] [--with-docs] [--offline]
Add a module or repository to your project. VPM’s internal parser will identify and configure any subdependencies.
Options:
--repo: Treat the URL as a full repository instead of a single module--riscv: Include RISC-V specific modules--commit <HASH>: Specify a commit hash to include--with-docs: Create documentation for the module--offline: Generate documentation in offline mode (only if —with-docs is set)
docs
Usage: vpm docs <MODULE_PATH> [--from-repo] [--offline]
Generate documentation for a module. This command creates comprehensive documentation for the specified module, including descriptions of inputs, outputs, and functionality.
Options:
--from-repo: Treat the module path as a link to a .v or .sv file in a GitHub repository--offline: Generate documentation in offline mode for code security
install
Usage: vpm install <TOOL_NAME>
Install a specified tool. VPM automates the build process and installs missing subdependencies.
Available tools: verilator, iverilog, yosys, gtkwave, verible, edalize, riscv-gnu-toolchain
update
Usage: vpm update <MODULE_PATH> [--commit <HASH>]
Update a specific module to its latest version. This command checks for updates to the specified module and applies them if available.
Options:
--commit <HASH>: Update to a specific commit hash
remove
Usage: vpm remove <PACKAGE_PATH>
Remove a package from your project. This command uninstalls the specified package and removes it from your project’s dependencies.
list
Usage: vpm list
List all available modules in the current project.
sim
Usage: vpm sim <FILE_PATHS>... [--waveform]
Simulate one or more Verilog files. Include ‘_tb’ in the testbench file name; otherwise, a base testbench and waveform will be generated.
Options:
--waveform: Generate waveform output and open it in GTKWave
synth
Usage: vpm synth <TOP_MODULE_PATH> [--riscv] [--core-path <PATH>] [--board <BOARD>] [--gen-yosys-script]
Synthesize a top module. This command performs synthesis on the specified top module, converting your RTL design into a gate-level netlist.
Options:
--riscv: Set this flag for RISC-V based designs--core-path <PATH>: Path to RISC-V core (required if —riscv is set)--board <BOARD>: Specify target board (xilinx, altera, custom)--gen-yosys-script: Generate a Yosys synthesis script instead of running synthesis
load
Usage: vpm load <TOP_MODULE_PATH> <CONSTRAINTS_PATH> [--riscv]
Load a top module onto a target device. This command programs the synthesized design onto the specified hardware.
Options:
--riscv: Use RISC-V toolchain for loading
run
Usage: vpm run <PROGRAM_PATH> [--riscv]
Run a specified program. This command executes the given program, which can be useful for running custom scripts, tools, or compiled designs.
Options:
--riscv: Use RISC-V toolchain for running the program
upgrade
Usage: vpm upgrade
Upgrade VPM to the latest version available.
config
Usage: vpm config [--analytics <BOOL>]
Configure VPM settings. This command allows you to set various options and preferences for VPM.
Options:
--analytics <BOOL>: Enable or disable anonymous usage data collection
test
Usage: vpm test <MODULE_PATH>
Create testbenches, run simulations, and generate waveform images for a module.